library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.typeDefinitions.all;

entity instDecode is
  
  port (
    fnct : in std_logic_vector(5 downto 0);
    opcode : in std_logic_vector(5 downto 0);
    op : out operation
   );

end instDecode;

architecture arch of instDecode is
begin

  decode : process (opcode, fnct)
  begin  -- process decode
    op <= o_addu;
    case TO_INTEGER(unsigned(opcode)) is
      when 0 =>
        case TO_INTEGER(unsigned(fnct)) is
          when 0 =>
            op <= o_sll;
          when 2 =>
            op <= o_srl;
          when 8 =>
            op <= o_jr;
          when 33 =>
            op <= o_addu;
          when 35 =>
            op <= o_subu;
          when 36 =>
            op <= o_and;
          when 37 =>
            op <= o_or;
          when 38 =>
            op <= o_xor;
          when 39 =>
            op <= o_nor;
          when 42 =>
            op <= o_slt;
          when 43 =>
            op <= o_sltu;
          when others =>
            op <= o_halt;  --hope we never hit this. Unsupported op
        end case;
      when 2 =>
        op <= o_j;
      when 3 =>
        op <= o_jal;
      when 4 =>
        op <= o_beq;
      when 5 =>
        op <= o_bne;
      when 9 =>
        op <= o_addiu;
      when 10 =>
        op <= o_slti;
      when 11 =>
        op <= o_sltiu;
      when 12 =>
        op <= o_andi;
      when 13 =>
        op <= o_ori;
      when 14 =>
        op <= o_xori;
      when 15 =>
        op <= o_lui;
      when 35 =>
        op <= o_lw;
      when 43 =>
        op <= o_sw;
      when 48 =>
        op <= o_ll;
      when 56 =>
        op <= o_sc;
      when others =>
        op <= o_halt;                   --invalid op
    end case;
    
  end process decode;
  
end arch;
